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Espressif Systems /ESP32-S3 /APB_SARADC /THRES1_CTRL

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Interpret as THRES1_CTRL

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https://regviz.com/r/Espressif Systems/ESP32-S3/APB_SARADC/THRES1_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0THRES1_CHANNEL 0THRES1_HIGH0THRES1_LOW

Description

configure apb saradc thres monitor

Fields

THRES1_CHANNEL

configure which channel thres0 monitor
THRES1_HIGH

thres1 monitor high thres
THRES1_LOW

thres1 monitor low thres

Links

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data